Stress Issue of Vertical Connections in 3D Integration for High-Bandwidth Memory Applications

Abstract

The stress of TSV with different dimensions under annealing condition has been investigated. Since the application of TSV and bonding technology has demonstrated a promising approach for vertical connection in HBM stacking, the stress caused by Cu TSV substrates needs to be carefully investigated. The changing in TSV size under the same TSV aspect ratio does not obviously affect the stress toward the surroundings. On the other hand, the adjustment on TSV aspect ratios results in different stress values, and the aspect ratio of 1:8 results in the largest stress in the analysis. Besides, the annealing temperature has more influence on the stress than the size of TSV. As a consequence, reduction on the annealing temperature is an effective method to achieve a low stress for TSV in HBM stacks. Therefore, several methods for low temperature hybrid bonding have also been reviewed and discussed.

Keywords

• HBM packaging
• Stress
• TSV simulation