Extremely large area (88 mm × 88 mm) superconducting integrated circuit (ELASIC)

Abstract

Abstract Superconducting integrated circuit is a promising “beyond-CMOS” device technology enables speed-of-light, nearly lossless communications to advance cryogenic (4 K or lower) computing. However, the lack of large-area superconducting IC has hindered the development of scalable practical systems. Herein, we describe a novel approach to interconnect 16 high-resolution deep UV (DUV EX4, 248 nm lithography) full reticle circuits to fabricate an extremely large (88 mm × 88 mm) area superconducting integrated circuit (ELASIC). The fabrication process starts by interconnecting four high-resolution DUV EX4 (22 mm × 22 mm) full reticles using a single large-field (44 mm × 44 mm) I-line (365 nm lithography) reticle, followed by I-line reticle stitching at the boundaries of 44 mm × 44 mm fields to fabricate the complete ELASIC field (88 mm × 88 mm). The ELASIC demonstrated a 2X–12X reduction in circuit features and maintained high-stitched line superconducting critical currents. We examined quantum flux parametron circuits to demonstrate the viability of common active components used for data buffering and transmission. Considering that no stitching requirement for high-resolution EX4 DUV reticles is employed, the present fabrication process has the potential to advance the scaling of superconducting qubits and other tri-layer junction-based devices.