Design and analysis of an efficient low power low delay low leakage clock keeper domino logic

Abstract

The design and development of CMOS VLSI semiconductor circuits employing deep sub-micron technology has faced significant challenges, primarily in terms of propagation delay and power consumption. This work introduces a new method called low leakage clock keeper domino logic (LLCKDL) for creating CMOS logic gates. The purpose of this approach is to decrease the amount of power consumed via leakage and enhance the efficiency of the gates in terms of noise. Existing and suggested methodologies can be employed to develop 16-bit input OR gates and simulated using GPDK 45 nm CMOS technological node in Cadence with a clock frequency of 10 MHz. The simulation results have been assessed by comparing the power usage, unity noise gain (UNG) and propagation latency. The Simulation outcomes show that the average power usage for the suggested domino has been improved to 87.12 %, 89.83 %, 93.38 %, 90.24 %, 86.4 %, and 88.01 % concerning CEDL, CMFD, CSK-DL, HSCD, FDSTDL and GPKD respectively. The delay for the suggested design has been improved to 42.66 %, 56.31 %, 29.97 %, 18.18 %, 11.25 %, and 16.95 % concerning CEDL, CMFD, CSK-DL, HSCD, FDSTDL, and GPKD respectively. The PDP for the suggested design has been improved to 92.62 %, 95.56 %, 95.37 %, 92.02 %, 87.94 % and 90.05 % concerning CEDL, CMFD, CSK-DL, HSCD, FDSTDL and GPKD respectively. The EDP for the suggested design has been improved to 95.78 %, 98.06 %, 96.76 %, 93.49 %, 89.28 % and 91.76 % concerning CEDL, CMFD, CSK-DL, HSCD, FDSTDL and GPKD respectively.

Keywords

• Power consumption
• Delay
• Domino logic
• GPDK 45 nm
• CMOS