Ethernet Packet-to-RS485 Data Transfer Bridge Application-Specific Integrated Circuit Incorporating Transmission Control Protocol and Static Random-Access Memory

Abstract

This paper proposes a high-throughput application-specific integrated circuit (ASIC) designed for bridging Ethernet packets and RS485 data, featuring a transmission control protocol (TCP) and static random-access memory (SRAM). The bridge ASIC complies with a 1-gigabit media-independent interface (GMII) and media-independent interface protocol standards. As the Ethernet receiver (RX) receives an Ethernet packet from GMII, it stores the TCP header and payload data in the SRAM. Next, the RS485 module reads the data stored in the SRAM for transmission to a computer through an RS485-to-universal serial bus cable. The Ethernet transmitter (TX) reads the TCP header and payload data from the SRAM and forms a complete Ethernet packet by adding the source address, destination address, and Internet protocol header. Passing through the GMII device, the complete Ethernet packet is sent to the Ethernet port, which is connected to a computer with an RJ45 network cable. This study was validated using NC-Verilog software and a field-programmable gate array board (DE10-Standard). After successful verification, the ASIC was fabricated using the Taiwan Semiconductor Manufacturing Company 0.18- $\mu $ m complementary metal-oxide semiconductor process. The simulated and measured results indicate that the throughput, processing latency, power consumption, gate count, and chip area are 844.88 Mbps, $139.31~\mu $ s, 134.79 mW, 69287, and $1.19\times 1.19$ mm2, respectively, under an operating frequency of 125 MHz, on-chip SRAM of 256 bytes, and power supply voltage of 1.8 V. The key contribution not only reduces the size of the RS485-to-Ethernet module but also improves the performance and saves the chip cost.

Keywords

• Ethernet packet
• RS485 data
• transmission control protocol
• static random-access memory
• media-independent interface (MII)
• FPGA board