Parasitic Coupling in 3D Sequential Integration: The Example of a Two-Layer 3D Pixel
Petros Sideris,
Arnaud Peizerat,
Perrine Batude,
Gilles Sicard,
Christoforos Theodorou
Affiliations
Petros Sideris
University Grenoble Alpes, Univ. Savoie Mont Blanc, Centre National de la Recherche Scientifique (CNRS), Grenoble INstitut Polytechnique (Grenoble INP), Institut de Microélectronique Electromagnétisme Photonique-LAboratoire d′Hyperfréquences et de Caractérisation (IMEP—LAHC), 38000 Grenoble, France
Arnaud Peizerat
Commissariat à l’Energie Atomique et aux Energies Alternatives—Laboratoire d′Electronique des Technologies de l′Information (CEA—LETI), University Grenoble Alpes, 38054 Grenoble, France
Perrine Batude
Commissariat à l’Energie Atomique et aux Energies Alternatives—Laboratoire d′Electronique des Technologies de l′Information (CEA—LETI), University Grenoble Alpes, 38054 Grenoble, France
Gilles Sicard
Commissariat à l’Energie Atomique et aux Energies Alternatives—Laboratoire d′Electronique des Technologies de l′Information (CEA—LETI), University Grenoble Alpes, 38054 Grenoble, France
Christoforos Theodorou
University Grenoble Alpes, Univ. Savoie Mont Blanc, Centre National de la Recherche Scientifique (CNRS), Grenoble INstitut Polytechnique (Grenoble INP), Institut de Microélectronique Electromagnétisme Photonique-LAboratoire d′Hyperfréquences et de Caractérisation (IMEP—LAHC), 38000 Grenoble, France
In this paper, we present a thorough analysis of parasitic coupling effects between different electrodes for a 3D Sequential Integration circuit example comprising stacked devices. More specifically, this study is performed for a Back-Side Illuminated, 4T–APS, 3D Sequential Integration pixel with both its photodiode and Transfer Gate at the bottom tier and the other parts of the circuit on the top tier. The effects of voltage bias and 3D inter-tier contacts are studied by using TCAD simulations. Coupling-induced electrical parameter variations are compared against variations due to temperature change, revealing that these two effects can cause similar levels of readout error for the top-tier readout circuit. On the bright side, we also demonstrate that in the case of a rolling shutter pixel readout, the coupling effect becomes nearly negligible. Therefore, we estimate that the presence of an inter-tier ground plane, normally used for electrical isolation, is not strictly mandatory for Monolithic 3D pixels.
