Implementation architecture of signal processing in pulse Doppler radar system based on FPGA

Abstract

A kind of high speed and parallel hardware architecture is proposed and designed for digital signal processing of high frequency Pulse Doppler radar here. The platform is based on one XC7K410T FPGA, two XC7K325T FPGAs, one TMS320C6678 DSP, and four sets of MT41J256M8 DDR3. The details of implementation including pulse compression, moving target detection and constant-false-alarm rate are described. The simulation results and resource consumption are presented to demonstrate the advantages of the proposed FPGA implementation architecture.

Keywords

• object detection
• digital signal processing chips
• doppler radar
• field programmable gate arrays
• radar detection
• radar signal processing
• pulse compression
• parallel architectures
• pulse doppler radar system
• parallel hardware architecture
• digital signal processing
• high frequency pulse doppler radar
• tms320c6678 dsp
• mt41j256m8 ddr3
• constant-false-alarm rate
• fpga implementation architecture
• xc7k410t fpga
• xc7k325t fpga
• pulse compression
• moving target detection
• resource consumption