Energy-Performance Optimization via P/N Ratio Sizing With Full Diffusion Layout Structure and Standard Cell Height Tuning in Near-Threshold Voltage Operation

Abstract

In recent decades, near-threshold voltage (NTV) design has become a well-known technique for improving the energy efficiency of digital integrated circuits. However, scaling down the operating voltage to the NTV raises two major challenges for robust operation: process variability and performance degradation. In this study, we propose a joint optimization technique for standard cell design to address the challenge of performance degradation in NTV design. The standard cell P/N ratio (PMOS width to NMOS width ratio) is being sized to maximize the performance with the constraint of a full diffusion (FD) layout structure, and the standard cell height is jointly optimized to further improve the circuit’s performance or energy consumption. Increasing the standard cell height improves the circuit performance at the cost of higher energy consumption, whereas lowering the standard cell height sacrifices the circuit’s performance for better energy saving. The results showed that implementing the taller library (14-track) in an AMBA high-speed bus (AHB) controller circuit can improve performance by up to 4.5%. The shortest library (7-track) resulted in 55% energy savings in the same circuit implementation. The test chip fabricated in 110-nm CMOS technology demonstrated successful operation of 8051 microcontroller down to 0.6V with the custom-designed 7-track library. The measurement results showed 4.3X energy saving compared to the operation at a supply voltage of 1.2V.

Keywords

• CMOS digital integrated circuit
• energy efficiency
• near-threshold voltage
• P/N ratio optimization
• standard cell height