Sensors (Apr 2018)

Design and Performance of a 1 ms High-Speed Vision Chip with 3D-Stacked 140 GOPS Column-Parallel PEs †

  • Atsushi Nose,
  • Tomohiro Yamazaki,
  • Hironobu Katayama,
  • Shuji Uehara,
  • Masatsugu Kobayashi,
  • Sayaka Shida,
  • Masaki Odahara,
  • Kenichi Takamiya,
  • Shizunori Matsumoto,
  • Leo Miyashita,
  • Yoshihiro Watanabe,
  • Takashi Izawa,
  • Yoshinori Muramatsu,
  • Yoshikazu Nitta,
  • Masatoshi Ishikawa

DOI
https://doi.org/10.3390/s18051313
Journal volume & issue
Vol. 18, no. 5
p. 1313

Abstract

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We have developed a high-speed vision chip using 3D stacking technology to address the increasing demand for high-speed vision chips in diverse applications. The chip comprises a 1/3.2-inch, 1.27 Mpixel, 500 fps (0.31 Mpixel, 1000 fps, 2 × 2 binning) vision chip with 3D-stacked column-parallel Analog-to-Digital Converters (ADCs) and 140 Giga Operation per Second (GOPS) programmable Single Instruction Multiple Data (SIMD) column-parallel PEs for new sensing applications. The 3D-stacked structure and column parallel processing architecture achieve high sensitivity, high resolution, and high-accuracy object positioning.

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