High‐speed, two‐stage operational transconductance amplifier without Miller capacitor, suitable for large capacitive load

Abstract

Abstract A two‐stage Class A‐AB operational transconductance amplifier with low power consumption, high slew rate, and high bandwidth is introduced for handling large capacitive loads. Unlike the conventional two‐stage operational transconductance amplifiers that use a Miller capacitor, compensation is provided by the load capacitor (CL) at the output node. The proposed two‐stage amplifier maintains a 45° phase margin (PM) over any load capacitance. This is achieved through a MOSFET‐based RC network at the output node. Dual nMOS/pMOS differential stages drive output directly, improving both SR+ and SR−. Post‐layout simulation results with a capacitive load of 100 pF (CL) demonstrate that the proposed operational transconductance amplifier has a DC gain of 60.1 dB, an excellent average slew rate of 20.3 V/µs, a gain‐bandwidth product of 10.6 MHz, an average 1% settling time of 122.2 ns and a PM of 76.6°, while consuming only 103.5 µW. Reducing the CL to 10 pF reduces the PM to 47.6°, while increasing the gain‐bandwidth and average slew rate to 82.9 MHz and 142.6 V/µs respectively.

Keywords

• analogue circuits
• CMOS analogue integrated circuits