SOI nanodevices and materials for CMOS ULSI

Abstract

A review of recently explored new effects in SOI nanodevices and materials is given. Recent advances in the understanding of the sensitivity of electron and hole transport to the tensile or compressive uniaxial and biaxial strains in thin film SOI are presented. The performance and physical mechanisms are also addressed in multi-gate Si, SiGe and Ge MOSFETs. The impact of gate misalignment or underlap, as well as the use of the back gate for charge storage in double-gate nanodevices and of capacitorless DRAMare also outlined.

Keywords

• ballistic transport
• gate misalignment
• GIFBE
• mobility enhancement
• SOI
• strain engineering