FPGA implementation of an arbitrary resample rate, FOH, pulse width modulator

Abstract

This study presents a field-programmable gate array implementation of an advanced pulse-width modulator which combines a first-order hold (FOH) with phase accumulator carrier pulse-width modulation (PACPWM) for significantly reduced phase delay, and bandwidth extension in multi-level applications. The FOH block supports arbitrary resampling rates and operates in a single clock cycle for simple integration into multi-rate or asynchronous systems. The proposed modulator is validated experimentally, with performance matching that predicted for both FOH and a zero-order hold (ZOH). For PWM with 8 kHz carrier frequency and 50.4 kHz resampling frequency, a 15 degree phase delay advantage is demonstrated for FOH compared with ZOH across the 5–10 kHz modulation band.

Keywords

• field programmable gate arrays
• pulse width modulation
• asynchronous circuits
• field-programmable gate array implementation
• advanced pulse-width modulator
• first-order hold
• phase accumulator carrier pulse-width modulation
• reduced phase delay
• bandwidth extension
• FOH block
• arbitrary resampling rates
• single clock cycle
• asynchronous systems
• zero-order hold
• modulation band
• PACPWM
• frequency 8.0 kHz
• frequency 5.0 kHz to 10.0 kHz
• FOH
• frequency 50.4 kHz