Advanced Si solid phase crystallization for vertical channel in vertical NANDs
Sangsoo Lee,
Yong-Hoon Son,
Kihyun Hwang,
Yoo Gyun Shin,
Euijoon Yoon
Affiliations
Sangsoo Lee
Department of Materials Science and Engineering and Inter-university Semiconductor Research Center, Seoul National University, Seoul 151-742, South Korea
Yong-Hoon Son
Department of Materials Science and Engineering and Inter-university Semiconductor Research Center, Seoul National University, Seoul 151-742, South Korea
Kihyun Hwang
Semiconductor R&D Center, Samsung Electronics Co., Ltd., Hwasung 445-701, South Korea
Yoo Gyun Shin
Semiconductor R&D Center, Samsung Electronics Co., Ltd., Hwasung 445-701, South Korea
Euijoon Yoon
Department of Materials Science and Engineering and Inter-university Semiconductor Research Center, Seoul National University, Seoul 151-742, South Korea
The advanced solid phase crystallization (SPC) method using the SiGe/Si bi-layer structure is proposed to obtain high-mobility poly-Si thin-film transistors in next generation vertical NAND (VNAND) devices. During the SPC process, the top SiGe thin film acts as a selective nucleation layer to induce surface nucleation and equiaxial microstructure. Subsequently, this SiGe thin film microstructure is propagated to the underlying Si thin film by epitaxy-like growth. The initial nucleation at the SiGe surface was clearly observed by in situ transmission electron microscopy (TEM) when heating up to 600 °C. The equiaxial microstructures of both SiGe nucleation and Si channel layers were shown in the crystallized bi-layer plan-view TEM measurements. Based on these experimental results, the large-grained and less-defective Si microstructure is expected to form near the channel region of each VNAND cell transistor, which may improve the electrical characteristics.
