Exploration of underlap induced high-k spacer with gate stack on strain channel cylindrical nanowire FET for enriched performance

Abstract

Abstract This research explores a comprehensive examination of gate underlap incorporated strained channel Cylindrical Gate All Around Nanowire FET having enriched performances above the requirement of the 2 nm technology node of IRDS 2025. The device installs a combination of strain engineering based quantum well barrier system in the channel region with high-k spacers sandwiching the device underlaps and stack high-k gate-oxide. The underlaps are prone to parasitic resistance and various short channel effects (SCEs) hence, are sandwiched by HfO2 based high-k. This SCE degradations and a strong electric field in the drain-channel region is rendered controlling the leakages. The strain based Nanosystem engineering is incorporated with Type-II heterostructure band alignment inducing quantum well barrier mechanism in the ultra-thin cylindrical channel region creating an electrostatic charge centroid leading to energy band bending and splitting among the two-fold and four-fold valleys of the strained Silicon layer. This provides stupendous electron mobility instigating high current density and electron velocity in the channel. Thereby, the device is susceptible to on-current enhancement via ballistic transport of carriers and carrier confinement via succumbing of quantum charge carriers. The device transconductance, Ion, Ioff, Ion/Ioff ratio are measured and the output performance (ID-VDS) characteristics is determined providing emphatic enrichments in contrast to the existing gate all-around FETs as well as the 2 nm technology node data of IRDS 2025. Hence, the strained channel Nanowire FET device developed here is presented here as the device of the future for various digital applications, RF applications and faster switching speed.