An Alternative Level Enhanced Switching Angle Modulation Schemes for Cascaded H Bridge Multilevel Inverters

Muthukumar Paramasivan; K. Eswaramoorthy; Rathinam Muniraj; Padmasuresh Lekshmi Kanthan; Thanikanti Sudhakar Babu; S. Jeevananthan; Hassan Haes Alhelou

doi:10.1109/ACCESS.2023.3283253

IEEE Access (Jan 2023)

An Alternative Level Enhanced Switching Angle Modulation Schemes for Cascaded H Bridge Multilevel Inverters

Muthukumar Paramasivan,
K. Eswaramoorthy,
Rathinam Muniraj,
Padmasuresh Lekshmi Kanthan,
Thanikanti Sudhakar Babu,
S. Jeevananthan,
Hassan Haes Alhelou

Affiliations

Muthukumar Paramasivan: ORCiD; Department of Electrical and Electronics Engineering, Prasad V. Potluri Siddhartha Institute of Technology, Vijayawada, Andhra Pradesh, India
K. Eswaramoorthy: ORCiD; Department of Electrical and Electronics Engineering, Narsimha Reddy Engineering College, Secunderabad, Telangana, India
Rathinam Muniraj: Department of Electrical and Electronics Engineering, P. S. R. Engineering College, Sivakasi, Tamil Nadu, India
Padmasuresh Lekshmi Kanthan: ORCiD; Department of Electrical and Electronics Engineering, Baselios Mathews II College of Engineering, Sasthamcotta, Kollam, Kerala, India
Thanikanti Sudhakar Babu: ORCiD; Department of Electrical and Electronics Engineering, Chaitanya Bharathi Institute of Technology (CBIT), Hyderabad, Telangana, India
S. Jeevananthan: ORCiD; Department of Electrical and Electronics Engineering, Puducherry Technological University, Puducherry, India
Hassan Haes Alhelou: ORCiD; Department of Electrical and Computer Systems Engineering, Monash University, Clayton, VIC, Australia

DOI: https://doi.org/10.1109/ACCESS.2023.3283253
Journal volume & issue: Vol. 11
pp. 57365 – 57382

Abstract

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This paper suggests an alternate level enhancing algorithm to operate the nine-level cascaded multilevel inverter (CHBMLI) for a 31-level output, which involves an inventive selection of optimal asymmetrical voltage values in separate DC sources (SDCs) and a quarter-wave symmetry pulse pattern pulse width modulation (QSP-PWM). The symmetrical CHBMLI structure involves the same DCs with an objectionable value of component count, especially at higher level outputs; consequently, there is a need to reduce the component count. It can be supported largely by the optimal set of asymmetrical voltage values (say 1:2:4:8), such an actualization is quite easy with photovoltaic (PV) applications. Additionally, many of the commonly used PWM methods of MLI are tedious especially when it comes to the generation of pulses. This paper also engraves a straightforward switching strategy apposite to the developed MLI topology. In addition, three new switching angle modulation schemes have been proposed to get the optimum performance, namely, incremental delay switching angle modulation scheme, random delay switching angle modulation scheme and sine referencing-based switching angle modulation scheme. The preliminary study on the tenet of suggested topology is done theoretically, then the performance is analyzed in MATLAB2019a software and finally, experimentally corroborated on a proof-of-concept (POC) prototype with the aid of ModelSim6.3f hardware description language simulation environment, Xilinx 14.5 project navigator tool and XC3S500E field-programmable-gate-array processor. The tested results for the inductive load demonstrate the output voltage synthesizing and the total harmonic distortion curtailment savvies of the proposed MLI and the switching strategies.

Published in IEEE Access

ISSN: 2169-3536 (Online)
Publisher: IEEE
Country of publisher: United States
LCC subjects: Technology: Electrical engineering. Electronics. Nuclear engineering
Website: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639

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