Design and Simulation of Balanced Ternary Priority Encoder

Abstract

The priority encoder is a frequently used circuit in binary logic and is mostly used for interrupt handling and other priority resolving tasks. On the other hand, Ternary computing has tremendous potential for handling a wide variety of functions involving large range of numbers, whereas, the literature is confined to very basic functions. The proposed balanced priority encoder circuit that uses three logic symbols i.e. −1,0 and 1. In this study, we develop the design and architecture of a Ternary Priority Encoder circuit with an estimation of its time complexity. The intricacy of the circuit under consideration is supposed to highlight the capabilities of the ternary logic system. The flexibility of the circuit lies in its implementation using simple binary counterparts. As there is no simulator available for Ternary Logic, we have developed a Balanced Ternary Logic Simulator which is freely available from https://github.com/Aggtur11/Ternary-Logic-Simulator. The logic behaviour of the proposed priority encoder circuits is verified using the developed simulator.

Keywords

• Priority encoder
• Balanced ternary
• Input decoder
• Output decoder
• Ternary logic simulator