S-TAT Leakage Current in Partial Isolation Type Saddle-FinFET (Pi-FinFET)s

Abstract

In this paper, we compare conventional saddle type FinFETs to partial isolation type saddle FinFETs (Pi-FinFETs) using 3D TCAD simulations to examine the effect of single charge traps for proper prediction of leakage current. We simulated single charge traps at various locations in the drain region, and analyzed how the traps affect leakage current. Our results show that Pi-FinFETs enhanced the leakage current characteristics given the presence of a single charge trap. Also, it was found that Pi-FinFETs exhibit half the $\text{F}_{\mathrm {TAT}}$ of S-FinFETs. Based on the results from our analysis method, where we use $\text{I}_{\mathrm {off}}$ fluctuation, the $\text{F}_{\mathrm {TAT}}$ , the $\sigma _{\mathrm {F}}$ and the $\text{P}_{\mathrm {F}}$ parameters to accurately compare performance, and present device design guidelines aimed at improving DRAM refresh characteristics.

Keywords

• Partial isolation type FinFET (Pi-FinFET)
• potential drop width (PDW)
• band-to-band tunneling (BTBT)
• trap-assisted tunneling (TAT)
• gate-induced drain leakage (GIDL)
• on current (Ion)