Chip Power Scaling in Recent CMOS Technology Nodes

Abstract

This paper tracks the scaling of total chip power at constant frequency (i.e., energy-per-operation) through the last few CMOS nodes. The focus is on high-performance microprocessors. To evaluate the progression of chip power, Intel’s Core-i7 (Intel’s highest performance consumer microprocessor manufactured in the highest performance CMOS technology node) was used as the benchmark. Core-i7 has been manufactured for eight generations starting in the 45-nm node and continuing through the 14++ node. This paper argues that in the more recent nodes, the total chip power at constant frequency (energy-per-operation) has scaled much less than that of the earlier CMOS nodes. The early 14-nm technology exhibited particularly poor power scaling, and in fact, the technology was improved by increasing the device current and relaxation of the contacted gate pitch in 14++. Early product data in 10 nm points to issue in dropping the chip power (at constant frequency) relative to the previous node (14++), which may challenge the power-performance justification for scaling to the 10 nm node and beyond. Improving chip power scaling (energy-per-operation) in upcoming nodes is critical as a key part of the value proposition for continued CMOS scaling, especially as applied to high-performance microprocessors.

Keywords

• Computer performance
• CMOS scaling
• FinFET
• Moore’s law
• MOSFET
• power dissipation