Low‐power fast Fourier transform hardware architecture combining a split‐radix butterfly and efficient adder compressors

Abstract

Abstract Fast Fourier transform (FFT) is the most common low‐complexity implementation of the discrete Fourier transform, intensively employed to process real‐world signals in smart sensors for the internet of things. Butterflies play a central role as the FFT computing core data path since it calculates complex terms employing several multipliers. A low‐power FFT hardware architecture combining split‐radix decimation‐in‐time butterfly and 5‐2 adder compressors (ACs) is proposed and implemented. The circuits are described in Verilog hardware description language and synthesized using the Cadence Genus synthesis tool. The circuits are mapped onto a 65‐nm CMOS ST standard cell library. Results reveal that the proposed FFT hardware architecture using the split‐radix butterfly is 13.28% more power efficient than the radix‐4 one. The results further show that, by combining 5‐2 AC within the split‐radix butterfly, our proposal saves up to 43.1% of the total power dissipation considering the whole FFT hardware architecture, compared with the state‐of‐the‐art radix‐4 butterfly employing the adder automatically selected by the logic synthesis tool.

Keywords

• adders
• CMOS integrated circuits
• digital arithmetic
• discrete Fourier transforms
• fast Fourier transforms
• field programmable gate arrays