A Single-Ended Transmitter With Low Switching Noise Injection and Quadrature Clock Correction Schemes for DRAM Interface

Abstract

This paper presents a transmitter with a phase controller for low switching noise injection and a quadrature clock corrector (QCC) for correcting both phase error and duty cycle distortion of the divided quadrature clocks. The phase errors and the duty cycle distortions of the quadrature clocks determine the quality of the output DQS. The proposed QCC simultaneously runs phase correction and the duty adjustment of quadrature clocks for fast correction time. In order to reduce power switching noise induced by output drivers, the proposed transmitter transfers the data at different timings using the phase controller which generates the interpolated quadrature clocks for even and odd channels. Since the even channel is synchronized with the reference quadrature clocks and the odd channel is synchronized with the interpolated quadrature clocks, the peak switching currents consumed by output drivers are spread. The proposed circuit has been designed in 180-nm CMOS process using VDD of 1.8-V and VDDQ of 0.6-V and the target data rate is 3.2 Gbps. The corrected quadrature clocks have the duty cycle distortion of 0.2% and the phase error of 1.18° with input clock distortion. The output DQS of the transmitter shows the peak-to-peak jitter of 30.55-ps in the low switching noise injection mode with the phase offset of 122°, which is improved by 28.8% as compared to the normal mode.

Keywords

• DRAM
• transmitter (TX)
• double data rate (DDR)
• clock correction
• switching noise