Lower-Order Compensation Chain Threshold-Reduction Technique for Multi-Stage Voltage Multipliers
Francesco Dell’ Anna,
Tao Dong,
Ping Li,
Yumei Wen,
Mehdi Azadmehr,
Mario Casu,
Yngvar Berg
Affiliations
Francesco Dell’ Anna
Institute of Applied Micro-Nano Science and Technology—IAMNST, Chongqing Key Laboratory of Colleges and Universities on Micro-Nano Systems Technology and Smart Transducing, Chongqing Engineering Laboratoryfor Detection, Control and Integrated System, National Research Base of Intelligent Manufacturing Service, Chongqing Technology and Business University, Nan’an District, Chongqing 400067, China
Tao Dong
Faculty of Engineering, Science and Maritime Studies, Department of Microsystems, Campus Vestfold, Høgskolen i Sørøst-Norge, 235 3603 Kongsberg, Norway
Ping Li
Department of Instrumentation, School of Electronic Information and Electric Engineering, Shanghai Jiao Tong University, Shanghai 200240, China
Yumei Wen
Department of Instrumentation, School of Electronic Information and Electric Engineering, Shanghai Jiao Tong University, Shanghai 200240, China
Mehdi Azadmehr
Faculty of Engineering, Science and Maritime Studies, Department of Microsystems, Campus Vestfold, Høgskolen i Sørøst-Norge, 235 3603 Kongsberg, Norway
Mario Casu
Department of Electronics and Telecommunications (DET), Politecnico di Torino, Corso Duca degli Abruzzi No. 24, 10129 Torino, Italy
Yngvar Berg
Faculty of Engineering, Science and Maritime Studies, Department of Microsystems, Campus Vestfold, Høgskolen i Sørøst-Norge, 235 3603 Kongsberg, Norway
This paper presents a novel threshold-compensation technique for multi-stage voltage multipliers employed in low power applications such as passive and autonomous wireless sensing nodes (WSNs) powered by energy harvesters. The proposed threshold-reduction technique enables a topological design methodology which, through an optimum control of the trade-off among transistor conductivity and leakage losses, is aimed at maximizing the voltage conversion efficiency (VCE) for a given ac input signal and physical chip area occupation. The conducted simulations positively assert the validity of the proposed design methodology, emphasizing the exploitable design space yielded by the transistor connection scheme in the voltage multiplier chain. An experimental validation and comparison of threshold-compensation techniques was performed, adopting 2N5247 N-channel junction field effect transistors (JFETs) for the realization of the voltage multiplier prototypes. The attained measurements clearly support the effectiveness of the proposed threshold-reduction approach, which can significantly reduce the chip area occupation for a given target output performance and ac input signal.
