Hardware-accelerated real-time IP flow measurement method for multi-core architecture

Abstract

A hardware-accelerated real-time IP flow measurement method for multi-core architecture was proposed. IP datagrams were captured at wire speed of OC-192 links by FPGA. Data records were load balanced to the corresponding core-affinitive buffer queues to each processor core at flow level. Multi-stage hash values were used to detect collision when updating the flow table. Experiments show that this method can accelerate IP flow analysis effectively. With the input of 75 bytes packets, the system is able to process at wire speed of OC-192 links. This is of great significance to the online traffic identification and analysis of high speed backbones with large number of concurrent flows.

Keywords

• computer architecture
• network measurement
• hardware acceleration
• IP flow
• multi-core architecture
• FPGA