High Consistency Ramp Design Method for Low Noise Column Level Readout Chain

Abstract

In order to address the inconsistency problem caused by parasitic backend wiring among multiple ramp generators and among multiple columns in large-array CMOS image sensors (CIS), this paper proposes a high-precision compensation technology combining average voltage technology, adaptive negative feedback dynamic adjustment technology, and digital correlation double sampling technology to complete the design of an adaptive ramp signals inconsistency calibration scheme. The method proposed in this article has been successfully applied to a CIS with a pixel array of 8192(H) × 8192(V), based on the 55 nm 1P4M CMOS process, with a pixel size of 10×10μm2. The chip area is 88(H) × 89(V) mm2, and the frame rate is 10 fps. The column-level analog-to-digital converter is a 12-bit single-slope analog-to-digital converter (SS ADC). The experimental results show that the ramp generation circuit proposed in this paper can reduce the inconsistency among the ramp signals to 0.4% LSB, decreases the column fixed pattern noise (CFPN) caused by inconsistent ramps of each column to 0.000037% (0.15 e−), and increases the overall chip area and power consumption by only 0.6% and 0.5%, respectively. This method provides an effective solution to the influence of non-ideal factors on the consistency of ramp signals in large area array CIS.

Keywords

• CMOS image sensors
• single-slope ADC
• adaptive ramp signal generator
• correction of inconsistent error in ramp signals