A clock domain crossing multi-master-slave lightweight on-chip bus based on OCP

Abstract

The open core protocol (OCP) bus can be applied to decouple IP core functions and the interfaces to realize the plug-and-play function. Aiming at the synchronization problem when the OCP is connected to asynchronous clock domain, a lightweight synchronization interface is developed, which not only synchronizes the control signals but also reduces the hardware consumption caused by data buffer across the clock domain. In view of the scalability of the point-to-point OCP bus, the enhanced clock-domain-crossing OCP bus is deployed on the AMBA High-performance Bus (AHB)，which is interconnected by the shared bus, in order to realize multi-master-slave multi-clock transmission. It is proved by simulation that the enhanced clock-domain-crossing OCP-AHB bus can transmit data correctly, which is able to be rapidly deployed in the next step.

Keywords

• system on chip
• clock domain cross
• multiple master slave
• open core protocol