Common-Mode Voltage Reduction Method Based on Variable Sampling Frequency Finite Control Set-Model Predictive Control for PMSM Drive Systems

Abstract

In this article, a finite control set-model predictive control (FCS-MPC) with variable sampling time is proposed. A zero-voltage vector appears in the dead time between specific voltage vectors, resulting in an unintentionally large common-mode voltage. Herein, a large common-mode voltage was suppressed, and the load current was controlled using a voltage vector combination that did not cause a zero-voltage vector in dead time. Additionally, to improve the total harmonic distortion (THD) of the load current, the intersection of the predicted current and the command current by all the volage vectors (VVs) in the combination is confirmed. The VV where the intersection occurs is selected as the optimal VV. This optimal VV is applied to the point where the predicted current and the reference current intersect. The applicable range of the sampling time should be selected by considering the calculation time and number of switching. Through the proposed FCS-MPC strategy, not only can the common-mode voltage be limited to within ±Vdc/6, but an improved THD can also be obtained compared to the existing method using fixed sampling. The proposed method was verified through PSIM simulation and experimental results.

Keywords

• voltage source inverter (VSI)
• finite control set-model predictive control (FCS-MPC)
• common-mode voltage (CMV)