Comprehensive Hammering and Parasitic BJT Effects in Vertically Stacked DRAM

Abstract

This study investigates the row hammer tolerance and potential degradation by capacitive crosstalk (CC) and parasitic bipolar junction transistor (BJT) effect in vertically stacked dynamic random-access memory (VS-DRAM) using technology computer-aided design (TCAD) simulations. The close arrangement of word lines in VS-DRAM results in a subthreshold leakage by the CC effect. Furthermore, as VS-DRAM has a floating body, hole accumulation in the body occurs via gate-induced drain leakage (GIDL) at the storage node in the cell that stores ’1’. This can be accelerated by activating the bit-line (BL). The accumulated holes cause leakage current ( $I_{BJT}$ ) by the parasitic BJT when the BL state becomes low and it is found that $I_{BJT}$ can be enhanced by the CC effect in this study. The row hammer effect and $I_{BJT}$ by the CC and parasitic BJT effects can be mitigated by reducing Si width.

Keywords

• VS-DRAM
• capacitive crosstalk
• parasitic bipolar junction transistor
• floating body
• TCAD