Speed and area analysis on hierarchy multiplier

Abstract

This paper proposes designs of hierarchy multiplier by utilising different designs on 4:2 and 7:3 compressor and multiple compressors. The hierarchy multipliers is optimised in the term of speed or area of hierarchy multiplier by redesigning 4:2 compressor units and introducing a combination of 4:2 compressor and 7:3 compressor units in a Vedic multiplier block. All designs are simulated using Altera Quartus II software. The aim of this paper is to improve the performance in speed by moderately increasing the area without considering the power consumption. The proposed design is 4.5% to 8.3% faster and consumes -0.5% to 5.8% less area.