High-Performance NTRU Accelerator Using a Direct Memory Access Controller

Abstract

NTRU is a well-established and widely used public-key cryptography. It has been standardized in IEEE Std1363.1 and X9.98, and its variant was submitted to the National Institute of Standards and Technology (NIST) post-quantum cryptography (PQC) standardization contest. In this study, we proposed a high-performance accelerator implementation of the recent NTRU version submitted to the NIST PQC contest. In NTRU, there are two types of polynomials: ternary polynomial (TP) that has coefficients in $\{-1,0,1\}$ , and non-TP. In contrast to previous methods that support both multiplication of a TP and a non-TP and multiplication of non-TPs, the proposed accelerator performs only multiplication of non-TPs by converting a TP to a non-TP in advance. We also leveraged a direct memory access controller and simplified the definitions of the polynomial registers. Consequently, we reduced the latency, data transfer time, and resources, such as the need for a large number of registers and multiplexers. We synthesized the accelerator using 28-nm CMOS process technology. The results showed that the accelerator can perform encryption and decryption within 0.8 and $1.8~\mu $ s, respectively, at the maximum clock frequency of 1.67 GHz, requiring 494.9 k gate counts. Furthermore, the proposed accelerator demonstrated a higher performance with fewer resources than the existing accelerators.

Keywords

• Digital circuit
• post-quantum cryptography
• public-key cryptography