The design of three-input high-performance AND/XOR complex-gate circuit(三输入高性能AND/XOR复合门电路设计)

HUANGChunlei(黄春蕾); WANGLunyao(王伦耀); LIANGHao(梁浩); XIAYinshui(夏银水)

doi:10.3785/j.issn.1008-9497.2015.03.013

Zhejiang Daxue xuebao. Lixue ban (May 2015)

The design of three-input high-performance AND/XOR complex-gate circuit(三输入高性能AND/XOR复合门电路设计)

HUANGChunlei(黄春蕾),
WANGLunyao(王伦耀),
LIANGHao(梁浩),
XIAYinshui(夏银水)

Affiliations

HUANGChunlei(黄春蕾): Institute of Circuits and Systems, Ningbo University, Ningbo 315211, Zhejiang Province, China(宁波大学电路与系统研究所，浙江　宁波　315211)
WANGLunyao(王伦耀)
LIANGHao(梁浩): Institute of Circuits and Systems, Ningbo University, Ningbo 315211, Zhejiang Province, China(宁波大学电路与系统研究所，浙江　宁波　315211)
XIAYinshui(夏银水): Institute of Circuits and Systems, Ningbo University, Ningbo 315211, Zhejiang Province, China(宁波大学电路与系统研究所，浙江　宁波　315211)

DOI: https://doi.org/10.3785/j.issn.1008-9497.2015.03.013
Journal volume & issue: Vol. 42, no. 3
pp. 310 – 315

Abstract

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针对现有“与/异或”(AND/XOR)复合门级联设计电路存在功耗大、延时长等不足，提出一种基于晶体管级的三输入AND/XOR复合门电路结构.通过采用多轨结构、缩短传输路径以及混合CMOS逻辑设计方法，克服了原有电路中单一逻辑和单轨结构信号路径长的不足，进而提高了电路性能.在55 nm的CMOS技术工艺和PTM多种工艺下，经过HSPICE模拟和Cadence提取版图的后仿真，显示所设计的电路具有正确的逻辑功能，相较于采用门电路级联而成的AND/XOR电路，本电路在不同负载、频率和PVT组合等情况下的延时、功耗和功耗延迟积(PDP)都得到了明显改善.

Published in Zhejiang Daxue xuebao. Lixue ban

ISSN: 1008-9497 (Print)
Publisher: Zhejiang University Press
Country of publisher: China
LCC subjects: Science: Mathematics: Instruments and machines: Electronic computers. Computer science; Science: Physics
Website: https://www.zjujournals.com/sci/EN/1008-9497/home.shtml

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