Efficient storage method for FPGA-based partially parallel QC-LDPC decoder

Abstract

An efficient storage method of hard decisions sharing intrinsic and extrinsic memory banks for partially parallel QC-LDPC decoder was proposed.Extra memory banks for storing hard decisions were avoided in this method,which result in significantly reduced consumption of RAM resources and routed complexity.Implementation results based on a Xilinx XC2V6 000-5ff1 152 FPGA show that the proposed method improves the frequency and decodes throughput of the system,and significantly reduced the requirements for the number of BRAM.

Keywords

• LDPC code
• decoder
• partially parallel
• efficient storage
• FPGA implementation