A COMPREHENSIVE REVIEW ON LOW POWER FIXED WIDTH DIGITAL MULTIPLIER ARCHITECTURES

Abstract

In contemporary portable electronic devices featuring real-time DSP chips, a pivotal challenge lies in minimizing power consumption. The efficiency of these DSP chips is directly impacted by the substantial power dissipation of their multiplier sub-circuits. Consequently, numerous architectures emphasizing low-power consumption, high-speed operation, and compact layout structures for multiplier units have emerged in the literature over recent decades. This manuscript offers insights into select state-of-the-art fixed-width multiplier architectures tailored for low-power operation, presenting a detailed comparative analysis in terms of power consumption, area utilization, and processing delay. Notable among the fixed-width multiplier architectures are the serial, array, Vedic, Booth, Wallace-tree, and Modified Booth-Wallace designs. For operations involving larger operands, the Modified Booth-Wallace architecture is favored due to its reduced latency. This study concentrates on a comprehensive examination and evaluation of various low-power fixed-width multiplier architectures, highlighting diverse operand sizes. Simulation-based assessments utilizing the 45nm PTM model indicate that the Modified Booth-Wallace tree architecture achieves a 73% reduction in latency compared to a basic array multiplier. Moreover, CMOS-based designs demonstrate superior noise margin performance compared to GDI and CCGDI techniques. Notably, the dynamic voltage-controlled CCGDI-based architecture showcases a 60% enhancement in Power-Delay Product (PDP) compared to the conventional CMOS-based Modified Booth-Wallace multiplier architecture. The manuscript's novelty lies in its succinct overview of the latest multiplier architectures implemented at the 45nm technology node, specifically tailored for low-power DSP chips.

Keywords

• booth algorithm
• gdi
• low power vlsi
• multiplier