Ultrathin Encapsulation Strategies with Predefined Gate Dielectric Surface Area for Flexible Crystalline Silicon Nanomembrane-Based MOS Capacitors

Abstract

Ultrathin encapsulation strategies show huge potential in wearable and implantable electronics. However, insightful efforts are still needed to improve the electrical and mechanical characteristics of encapsulated devices. This work introduces Al2O3/alucone nanolaminates using hybrid atomic/molecular layer deposition for ultrathin encapsulation structures employed in crystalline silicon nanomembrane (Si NM)-based metal-oxide-semiconductor capacitors (MOSCAPs). The comprehensive electrical and mechanical analysis focused on the encapsulated and bare MOSCAPs with three gate dielectric diameters (Ø) under planar and bending conditions, including concave bending radii of 110.5 mm and 85 mm as well as convex bending radii of 77.5 mm and 38.5 mm. Combined with the Ø-related mechanical analysis of the maximum strain in the critical layers and the practical investigations of electrical parameters, the encapsulated MOSCAPs with Ø 160 μm showed the most stable electro-mechanical performance partly due to the optimized position of the neutral mechanical plane. Comparison of the electrical changes in Al2O3/alucone-encapsulated MOSCAPs with Ø 160 μm, Ø 240 μm, and Ø 320 μm showed that it is beneficial to define the gate dielectric surface area of 0.02 to 0.05 mm2 for Si NM-based wearable electronics. These findings are significant for leveraging the practical applications in ultrathin encapsulation strategies for reliable operations of crystalline Si NM-based integrated circuits.

Keywords

• ultrathin encapsulation
• silicon nanomembrane
• metal-oxide-semiconductor capacitors
• gate dielectric surface area