Development of Pilot-tone Based BPM Processor of Storage Ring

Abstract

Beam orbit stability is vital for the synchrotron radiation light source. Hefei Advanced Light Facility (HALF), the fourth generation diffraction limit storage ring now under preliminary research with submicron beam orbit stability, requires a beam position monitor (BPM) system with accuracy better than 100 nm. In this paper, a BPM processor with pilot tone was developed using domestic chips, which is composed of the pilot tone module, the analog frontend module, the digital processing module and the embedded control module. The input signals from BPM detector were adjusted in pilot tone module and analog frontend module, digitalized in digital processing module by bandpass sampling principle, and the digital signals were processed in FPGA (field programmable gata array) to obtain turnbyturn data, fast acquisition data (FA data) at a 10 kHz rate, and slow acquisition data (SA data) at a 10 Hz rate. The embedded control module transmitted the beam position information in real time and communicated with the accelerator control system. Thermal drifts of the channels and variations of the cables frequency response (due to changes in temperature or humidity) could introduce uncontrolled fluctuations in the position calculated. To enhance longterm stability of the BPM processor, a low phasenoise pilot tone was added to the beam signal as a reference to eliminate the effect of gain drifts of the individual channel on position calculation. The analog front end was customized with adjustable gain to increase the dynamic range of the system, and composed of four identical radiofrequency (RF) channels, each with several amplifiers, attenuators and filters to adjust the signals for ADC sampling. All beam position calculations were performed in the digital domain. The bandpass sampling technique was applied to convert narrowband RF signals into intermediatefrequency (IF) digital signals. And then the IF signals were converted to the baseband inphase and quadraturephase (IQ) data through the digital down conversion method. CIC (cascaded integrator comb) and FIR (finite impulse response) decimation filters were used to avoid highcomponent signal aliasing and decimate the IQ data rate. CORDIC (coordinated rotation digital computer) module was implemented in pipeline structure to calculate the signal amplitudes from IQ data. With four BPM signal amplitudes, the beam position could be obtained by the differenceoversum algorithm. These digital signal processing algorithms were integrated on one FPGA. At present, the laboratory offline tests and the beam tests of the designed beam position processor were carried out. The offline tests demonstrate the effectiveness of pilot tone in compensating for external changes and improving the longterm stability. The test results indicate that the resolutions of the FA data and SA data are better than 120 nm and 70 nm respectively with the input amplitudes ranging from -55 dBm to 5 dBm, which meet the design requirements.

Keywords

• bpm processor
• digital signal processing
• pilot-tone
• fpga
• domestic chip