Applying Genetic Algorithm for test pattern generation process optimization

Abstract

Objective. Comprehensive integrated circuit (IC) verification plays a crucial role in preventing costly errors and delays in product development cycle. It includes testing interaction and compatibility of different system elements, such as central processing unit, memory and various peripheral devices. Validating IC’s compliance to the functional requirements list may take up to 70% of the design process duration. This proportion grows with complexity and size of the device under development. Consequently, the essential tasks that integrated circuit developers face are research and development of methods for cutting design complexity and reducing implementation time.Method. Conducted research regarding usage of genetic algorithm for error discovery, which could lead to a failure in the end product.Result. Collected data regarding the amounts of victims and target errors for each fault of types stuck-at-0 and stuck-at-1 for circuits from ISCAS’85 and ISCAS’89 benchmarks. It has been discovered that the proposed method is more effective in comparison to random vector generation to an extent of target errors amount for every benchmark.Conclusions. Accumulated results allow for the algorithm usage during IC design in order to reduce time consumption for circuitry validation and improve on test kits quality.

Keywords

• faults
• logical circuits
• atpg
• genetic algorithm
• stuck-at-fault
• fault coverage