Research on 1 GS/s，16-bit data acquisition system based on JESD204B

Abstract

The paper adopts the architecture of "ADC+FPGA", designs and develops a 1 GS/s, 16-bit high-speed and high-precision data acquisition system(DAS), which realized the purpose of using a single channel to measure large dynamic range(DR>1 000) signals. The study uses two sysref modes, which are periodic sysref mode and pulse sysref mode, to establishe a stable JESD204B link with a deterministic delay. The differences in the sampled data spectrum between the two modes is presented, and the considerations of hardware design and firmware design are given. The paper recommends that the periodic sysref mode be used to establish JESD204B link. By analyzing the time-domain waveform and frequency spectrum of the sampled data, the conclusion that the ADC chip contains 4 on-chip ADC channels is verified.

Keywords

• data acquisition system
• jesd204b
• deterministic delay
• period sysref
• pulse sysref