CNFET-OCL: Open-Source Cell Libraries for Advanced CNFET Technologies

Abstract

In this paper, we propose CNFET-OCL, the first open-source cell libraries for 5-nm and 7-nm carbon nanotube field-effect transistor (CNFET) technologies. Our CNFET-OCL is designed to emulate the predictive 5-nm and 7-nm CNFET technologies presented in a published paper. We achieved this by performing a number of SPICE simulations based on an open-source CNFET SPICE model and making certain assumptions used in previous work. Each of our cell libraries includes two types of delay model (i.e., the composite current source and nonlinear delay model), each having 56 typical standard cells, which is sufficient to design various VLSI circuits. CNFET-OCL fully supports both logic synthesis and timing-driven place and route design in the Cadence design flow. Our experimental results demonstrate that CNFET-OCL can achieve performance levels comparable to those reported in previous studies on CNFETs. Consequently, CNFET-OCL can serve as an effective evaluation tool for the CNFET research community.

Keywords

• CNFET
• cell library
• logic synthesis
• place and route