An ultra-low-power processor pipeline-structure

Abstract

With the rapid development of communication and chip technology, IoT will be an important part of the next generation of information technology, a powerful driving force to promote the intelligent process of our lives. Among the IoT terminal applications, ultra-low-power microcontroller plays an indispensable role. Based on the design goal of ultra-low-power embedded applications, this paper proposes a pipeline structure of a processor based on RISC-V instruction set architecture. Taking into account the compromise between power consumption and performance, the main body uses a two-stage pipeline, and was supplemented by a pipeline structure with variable length of other components. The logic function of the microcontroller is verified in the VCS environment. At the same time, the area ratio report of the microcontroller is obtained by using the SMIC180 process library to complete the simulation in the DC environment. Finally, by running the running subroutine test and comparing it with the ARM Cortex-M microcontroller, the comparison results show that this work can also be applied to the low-power scene of IoT.

Keywords

• pipeline-structure
• ultra-low-power
• RISC-V architecture
• RISC-V processor