An Approach to <inline-formula> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula>-Stage Balanced-to-Single- Ended Out-of-Phase Power Divider With Enhanced Operating Bandwidth

Abstract

In this paper, an approach to n-stage (n= 3, 4, 5...) balanced-to-single-ended out-of-phase power divider is proposed, which enhances the bandwidths for port matching, isolation and common-mode suppression firstly. Compared with the traditional single-ended multistage power divider, this approach has special circuits (common-mode and isolation circuits) for improving common-mode suppression and isolation, respectively. For common-mode suppression, the 180° microstrip line between the balanced port and the common-mode circuit composed by one parallel open stub are adopted to achieve wideband common-mode suppression. For isolation, the isolation circuits formed by cascade stage structure and parallel resistors are both adopted to improve the isolation bandwidth. The basic analysis at the center frequency is given, and for verifying the theoretical prediction, two prototypes of the 3-and 4-stage power dividers are fabricated and measured, which show 46.7% and 63% 20-dB operating bandwidths, and 0.25 dB and 0.3 dB minimum insertion loss, respectively. These two prototypes present that the 20-dB operating bandwidths are 16.7% and 33% wider than the single-stage balanced-to-single-ended power divider.

Keywords

• Balanced-to-single-ended
• common-mode suppression
• isolation
• n-stage%22%2C%22default_operator%22%3A%22AND%22%7D%7D%7D"> <italic xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">n</italic>-stage
• out-of-phase
• power divider