Power estimation for intellectual property-based digital systems at the architectural level

Abstract

Estimating power consumption is becoming the critical issue that cannot be neglected in VLSI (very large scale integration) design procedure. Low power solutions are an imperative requirement for the SoC (System-on-Chip) flow that gives designers a powerful methodology to analyze, estimate, and optimize today’s increasing power concerns. We present an efficient power macro-modeling technique at the architectural level for digital electronic systems. This technique estimates the power dissipation of intellectual property (IP) components to their statistical knowledge of the primary inputs/outputs. During the power estimation method, the sequence of an input stream is generated by a genetic algorithm (GA) using input metrics and the macro-model function to construct a set of functions that map the input metrics of a macro-block to its output metrics. Then, a Monte Carlo zero-delay simulation is performed and the power dissipation is predicted by a macro-model function. The most important contribution of the technique is that it allows fast power estimation of IP-based design by the simple addition of individual power consumption. This makes the power modeling of SoCs an easy task that permits evaluation of power features at the architectural level. In order to evaluate our model, we have constructed IP-based digital systems using different IP macro-blocks. In experiments with an individual IP macro-block the average error is 1–2% and for an entire IP-based system with interconnects, the error range is from 9% to 15%. The preliminary results are effective and our macro-model provides accurate power estimation.

Keywords

• Digital system
• Intellectual property
• Genetic algorithm
• Power macro-modeling
• Look-up-table
• Register transfer level