A New Approach to Fourth-Order Quadrature Signal Generation for a Fast and Noise-Free PLL Output Under Non-Ideal Grid Voltage Conditions

Abstract

Dual quadrature signal generator (QSG) along with a positive sequence calculator (PSC) eliminates the negative sequence components from unbalanced grid voltages. The QSGs also offer attenuation to harmonics and dc-offset present in the sensed input voltages. Fourth-order QSGs offer superior harmonic attenuation with complete dc-offset rejection compared to lower-order QSGs. Therefore, dual fourth-order QSG + PSC is an apt solution for pre-filtering in phase-locked loops (PLLs) under non-ideal grid voltage conditions. Two fourth-order QSGs (FO-QSGs) namely, second-order SOGI-QSG (SO-SOGI-QSG) and cascaded SOGI-QSG have been proposed in the literature. Parameter selection for these FO-QSGs to achieve a faster dynamic response is challenging due to the higher order of the transfer functions. The response time of the QSGs directly impact the response time of the PLL. This paper proposes a new approach to fourth-order quadrature signal generation that achieves a lower settling time for the QSG compared to existing FO-QSGs. The proposed method achieves a faster response time by setting the QSG parameters using equations that directly relate to the system settling time. Using the proposed method, the QSG settles within 25.4 ms while maintaining a low total harmonic distortion.

Keywords

• Phase-locked loop
• non-ideal grid
• second-order generalized integrator
• quadrature signal generator