A 16.5-μW 73.7-dB-SNDR Second-Order Fully Passive Noise-Shaping SAR ADC With a Hybrid Switching Procedure

Abstract

Noise-shaping (NS) successive approximation register (SAR) analog-to-digital converters (ADCs) using passive integrators have drawn increasing attention owing to their simplicity and power efficiency. However, a capacitor array with a passive integrator result in a huge number of unit capacitors and power consumption. This paper presents a second-order fully passive NS-SAR ADC with a segmented capacitor array and a hybrid switching procedure. We use a most-significant-bit(MSB) sampling-segmented capacitor array to reduce the number of unit capacitors, and a common mode voltage(VCM)-based hybrid switching procedure to reduce the average switching power. Compared to fully passive NS-SAR ADCs with conventional capacitor array and switching procedure, the total number of unit capacitors is reduced by about 84%, and the average switching power is also reduced by about 97.8%. The prototype was fabricated using 180nm complementary metal oxide semiconductor(CMOS) technology, it only uses 478 unit capacitors, resulting in an area of 0.086 mm2. It consumes $16.5~\mu \text{W}$ , achieves 73.7 dB peak signal-to-noise-and-distortion ratio(SNDR), and a Schreier figure of merit(FoMs) of 165.5 dB.

Keywords

• Analog-to-digital converter (ADC)
• successive approximation register (SAR)
• segmented capacitor array
• noise-shaping (NS)
• hybrid ADC
• energy efficient