Area-efficient readout with 14-bit SAR-ADC for CMOS image sensors

Abstract

This paper proposes a readout design for CMOS image sensors. It has been squeezed into a 7.5um pitch under a 0.28um 1P3M technology. The ADC performs one 14-bit conversion in only 1.5us and targets a theoretical DNL feature about +1.3/-1 at 14-bit accuracy. Correlated Double Sampling (CDS) is performed both in the analog and digital domains to preserve the image quality.

Keywords

• CMOS Image Sensor
• Successive-Approximation-Register ADC
• Column-parallel architecture
• CDS