Controlled SOI nanopatterning for GaN pendeo-epitaxy

Abstract

Nanopatterning of GaN/AlN layers on Silicon-On-Insulator (SOI) substrates is discussed with the aim of fabricating nanopillar arrays that can be used for subsequent GaN pendeo-epitaxy. The principle of the developed epitaxy process is that GaN crystallites are grown on deformable nano-pedestals able to rotate at GaN growth temperature. The objective is to control the complete pattern profile of GaN/AlN/Si/SiO2 pillars, both in lateral and vertical directions. Since a smaller pillar diameter should enhance the pillar rotation at growth temperature, special emphasis will be given to nanometer-scale pillars. In this context, the control of GaN/AlN vertical sidewalls is still an issue for high-resolution nanopillars. In this paper, we report on the optimization of the plasma etching processes of GaN/AlN/Si/SiO2 stacks to reduce the slope that widens the pillar base. Overall, we achieve near perfect arrays of 100 nm diameter nanopillars obtained by combining NanoImprint Lithography (NIL) and plasma etching, with bases of 150 nm in diameter.

Keywords

• GaN/SOI nanopatterning
• Nanoimprint lithography
• Inductively coupled plasma
• Highresolution 100 nm nanopillars
• GaN pendeoepitaxy
• Future microLEDs