Low‐power hybrid memristor‐CMOS spiking neuromorphic STDP learning system

Abstract

Abstract An electronic circuit that implements a neural network architecture with spike neurons was studied, proposed, and evaluated, primarily considering energy consumption. In this way, CMOS transistors were used to implement neurons, memristors were used to work as synapses, and the proposed network has a spike‐timing‐dependent plasticity (STDP) learning aspect. The validation of the circuit modules and the complete network architecture was performed using SPICE models. Since most data of company technologies is restricted, some universities provide predictive models to reproduce the real ones. In this paper, two types of Integrate and Fire Neuron (I&F) using 32 nm CMOS technology simulated in LTspice with BSIM4v4 model designed by Berkley University and applying predictive parameters provided by Predictive Technology Model (PTM) are presented. The simulation results obtained here reduces the bias voltage and the chip size to the most recent designs implemented. Finally, communication between neurons and synapses with STDP learning has been successfully simulated.

Keywords

• circuit simulation
• CMOS integrated circuits
• learning (artificial intelligence)
• low-power electronics
• neural chips
• neural nets