Design of Capacitorless DRAM Based on Polycrystalline Silicon Nanotube Structure

Abstract

In this study, a capacitorless one-transistor dynamic random-access memory (1T-DRAM) based on a polycrystalline silicon nanotube structure with a grain boundary (GB) is designed and analyzed using technology computer-aided design (TCAD) simulation. The proposed 1T-DRAM has the improved electrical performances because the outer gate (OG) and the inner gate (IG) effectively control the charges in the channel and body regions. IG has an asymmetric structure with an underlap ( $L_{\mathrm {underlap}}$ ) region to reduce the Shockley–Read–Hall (SRH) recombination rate. In the proposed 1T-DRAM, the write “1” operation is performed by band-to-band tunneling between the OG and the IG. The proposed 1T-DRAM cell exhibited a sensing margin of $422 ~\mu \text{A}/\mu \text{m}$ and a retention time of 120 ms at $T$ = 358 K.

Keywords

• Polycrystalline silicon
• one-transistor dynamic random-access memory
• grain boundary
• nanotube
• metal–oxide–semiconductor field-effect transistor
• dual-gate