Parallel Implementation of OpenVX Feature Extraction Functions in Programmable Processing Architecture

Abstract

Aiming at the mass computing and slow speed of serial structure calculation of digital image processing, parallel implementation of underlying feature extraction kernel functions in the latest open source OpenVX specification 1.3 is completed, and the verification is carried out with the self-designed OpenVX programmable parallel processor. In the underlying feature extraction of the image, the basic pixel processing function Color Convert, the local image processing functions Gaussian Filter and Median Filter of OpenVX specification 1.3 are selected for filtering and smoothing. Harris Corners and Canny Edge Detector are selected for feature extraction. By dividing the complex nodes with large amount of computation into several simple nodes, different graph execution models are constructed and mapped on the OpenVX parallel processor to realize image edge detection and feature point extraction respectively. Verilog is used to design the hardware circuit, and the FPGA chip xcvu440-flga-2892-2-e of Xilinx has comprehensively verified that, compared with the serial mapping structure, the parallel acceleration ratio of the selected kernel function on the OpenVX programmable parallel processor can be up to 14.269. Experimental results show that the kernel functions in OpenVX specification 1.3, especially the complex kernel functions, can achieve expected acceleration effect in this parallel processing structure, and the speedup ratio of parallel and serial structures increases linearly.

Keywords

• |openvx specification 1.3|computer vision function|low level feature extraction|graph execution model|parallel processor