An 11 Gb/s 0.376 pJ/Bit Capacitor-Less Dicode Transceiver With Pattern-Dependent Equalizations TIA Termination for Parallel DRAM Interfaces

Abstract

This paper presents a capacitor-less dicode transceiver with pattern-dependent equalizations for parallel DRAM interfaces. The dicode signaling with dc-coupled transimpedance-amplifier (TIA) termination is adopted to minimize power dissipation. An reconfigurable asynchronous delay for equalization has been optimized at a data rate of 11 Gbps. To compensate for the offset voltage in the capacitor-less structure, mismatch calibration is implemented in both the TIA and the comparators. Monte-Carlo simulation shows that the standard deviation of the TIA offset voltage is reduced from 26.2 mV to 2.46 mV. At the transmitter side, an edge-delayed equalization is implemented for the dicode signaling. In the receiver, the dicode error correction circuit (ECC) is implemented to improve the bit error rate (BER). A silicon interposer channel of the high-bandwidth memory (HBM) is modeled using 6-mm on-chip metals. The dicode transceiver achieved a horizontal eye width of 0.421 unit interval (UI) at 11 Gbps with 0.376 pJ/bit.

Keywords

• Dicode signaling
• dynamic random access memory (DRAM)
• equalization
• error correction
• high-speed interface
• high bandwidth memory (HBM)