Journal of Engineering Science and Technology (Oct 2018)
AN EFFICIENT FULLY DIFFERENTIAL VOLTAGE COMPARATOR
Abstract
With the compactness of the devices, the circuits are required with less delay, less area and less power consumption. An efficient fully digital-in-notion differential voltage comparator with the opamp-less approach is implemented in this paper. This comparator detects a small input voltage difference, i.e., resolution of this comparator is 8-bits and amplifies the output to either of the two different logic levels high or low, i.e., 1 or 0 respectively. Though dynamic latched comparators are quite attractive, they suffer from high power consumption and large offset voltages. In addition to the low power consumption, this comparator is extremely cost-effective as an analogue circuit has been designed digitally and fabricated in a digital process. The comparator is designed and implemented in the Cadence Virtuoso tool using SCL 180 nm Complementary Metal Oxide Semiconductor (CMOS) digital process at a supply of 1.8 V and a load capacitance of 1 pF.