Data encoding techniques to improve the performance of System on Chip

Abstract

The concept of System on Chip (SoC) has introduced many opportunities but also many challenges and hurdles in Ultra Large Scale Integration (ULSI). In fact the global interconnects are undergoing a reverse scaling process in SoC which has resulted in a wider, thicker top metal layers and an increase in the wire aspect ratio. These impacts have increased the self and coupling capacitance of interconnects, leading to on-chip data communication to become more power consuming and less reliable. In this paper, an attempt has been made to propose two data encoding techniques namely 1) Odd-Even-Full-Normal inversion considering the total self and coupling switching activity (OEFNSC) 2) OEFNSC with segmentation (OEFNSC-SEG) to reduce the switching activity across self and coupling capacitance. These data encoding techniques have lead to the reduction of dynamic power and improve the reliability. The results proved the effectiveness of the proposed data-encoding schemes, in terms of Energy, Delay and Energy-Delay-Product efficiency of 8-bit, 16-bit, 32-bit and 64-bit respectively in 45 nm technology and these efficiencies have further improved by adopting the segmentation of proposed data encoding scheme.

Keywords

• Switching activity
• Crosstalk classes
• Data encoding
• Low power
• System on Chip (SoC)