Asymmetrical eleven‐level inverter topology with reduced power semiconductor switches, total standing voltage and cost factor

Abstract

Abstract Voltage source multilevel inverters (MLI) is widely utilized in medium and high‐power applications due to their advantages. Here, an 11‐level, asymmetrical multilevel inverter topology is proposed. The topology utilizes four unidirectional switches, three bidirectional switches along with two dc sources. The proposed configuration of switches and the concept of the dc‐link capacitor is utilized to generate eleven level output voltage. The reduced number of components such as power switches and DC sources, lower control complexity due to capacitors' self‐balancing nature, and low total standing voltage (TSV) are the critical features of the proposed topology. Moreover, a reliability assessment of the topology shows that the topology has a high mean time to fault (MTTF), which makes it robust and reliable. Matlab/Simulink environment is used to develop a simulation model of the proposed topology, while PLECS is used for the thermal modelling and analysis of the converter. A prototype is developed and tested in the laboratory to validate the performance for different loading conditions. The proposed topology can be cascaded to produce the ‘n’ number of levels. The critical comparison of the proposed topology shows that the proposed circuit has advantages over other compared topologies.