Synthesis of Self-Checking Circuits for Train Route Traffic Control at Intermediate Stations with Control of Calculations Based on Weight-Based Sum Codes
Dmitry V. Efanov,
Artyom V. Pashukov,
Evgenii M. Mikhailiuta,
Valery V. Khóroshev,
Ruslan B. Abdullaev,
Dmitry G. Plotnikov,
Aushra V. Banite,
Alexander V. Leksashov,
Dmitry N. Khomutov,
Dilshod Kh. Baratov,
Davron Kh. Ruziev
Affiliations
Dmitry V. Efanov
Laboratory “Industrial Stream Data Processing Systems”, Higher School of Mechanical Engineering, Material and Transport Institute, Peter the Great St. Petersburg Polytechnic University, St. Petersburg 195251, Russia
Artyom V. Pashukov
“Automation, Remote Control and Communication on Railway Transport” Department, Russian University of Transport, Moscow 127994, Russia
Evgenii M. Mikhailiuta
Laboratory “Industrial Stream Data Processing Systems”, Higher School of Mechanical Engineering, Material and Transport Institute, Peter the Great St. Petersburg Polytechnic University, St. Petersburg 195251, Russia
Valery V. Khóroshev
“Automation, Remote Control and Communication on Railway Transport” Department, Russian University of Transport, Moscow 127994, Russia
Ruslan B. Abdullaev
“Automation and Remote Control” Department, Tashkent State Transport University, Tashkent 100167, Uzbekistan
Dmitry G. Plotnikov
Laboratory “Industrial Stream Data Processing Systems”, Higher School of Mechanical Engineering, Material and Transport Institute, Peter the Great St. Petersburg Polytechnic University, St. Petersburg 195251, Russia
Aushra V. Banite
Laboratory “Industrial Stream Data Processing Systems”, Higher School of Mechanical Engineering, Material and Transport Institute, Peter the Great St. Petersburg Polytechnic University, St. Petersburg 195251, Russia
Alexander V. Leksashov
Laboratory “Industrial Stream Data Processing Systems”, Higher School of Mechanical Engineering, Material and Transport Institute, Peter the Great St. Petersburg Polytechnic University, St. Petersburg 195251, Russia
Dmitry N. Khomutov
Laboratory “Industrial Stream Data Processing Systems”, Higher School of Mechanical Engineering, Material and Transport Institute, Peter the Great St. Petersburg Polytechnic University, St. Petersburg 195251, Russia
Dilshod Kh. Baratov
“Automation and Remote Control” Department, Tashkent State Transport University, Tashkent 100167, Uzbekistan
Davron Kh. Ruziev
“Automation and Remote Control” Department, Tashkent State Transport University, Tashkent 100167, Uzbekistan
When synthesizing systems for railway interlocking, it is recommended to use automated models to implement the logic of railway automation and remote control units. Finite-state machines (FSMs) can be implemented on any hardware component. When using relay technology, the functional safety of electrical interlocking is achieved by using uncontrolled (safety) relays with a high coefficient of asymmetry of failures in types 1 → 0 and 0 → 1. When using programmable components, the use of backup and diverse protection methods is required. This paper presents a flexible approach to synthesizing FSMs for railway automation and remote control units that offer both individual and route-based control. Unlike existing solutions, this proposal considers the pre-failure states of railway automation and remote control units during the finite-state machine synthesis stage. This enables the implementation of self-checking and self-diagnostic modules to manage automation units. By increasing the number of states for individual devices and considering the states of interconnected objects, the transition graphs can be expanded. This expansion allows for the synthesis of the transition graph of the control subsystem and other systems. The authors used a field-programmable gate array (FPGA) to implement a finite-state machine. In this case, the proposal is to encode the states of a finite-state machine using weight-based sum codes in the residue class ring based on a given modulus. The best coverage of errors occurring at the outputs of the logic converter in the structure of the FSM can be ensured by selecting the weighting coefficients and the value of the module. This paper presents an example of synthesizing an FPGA-based FSM using state encoding through modular weight-based sum codes. The operation of the synthesized device was modeled. It was found to operate according to the same algorithm as the real devices. When synthesizing self-checking and self-controlled train control devices, it is recommended to consider the solutions proposed in this paper.
